1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to methods of removing resistor protect films from resistor structures.
2. Description of the Related Art
Modern integrated circuits routinely contain millions of individual circuit devices. Transistors and resistors represent two of the most commonly used types of such circuit devices. Although examples of various transistor designs used in semiconductor fabrication are legion, most consist of a gate electrode and one or more impurity regions. Resistor structures are similarly fabricated in a great variety of configurations. Some are fabricated by establishing impurity regions in a semiconductor substrate. Others are fabricated by fabricating silicon or polysilicon structures and thereafter selectively doping certain portions of those structures or leaving them in an undoped state.
In some conventional semiconductor manufacturing processes, the fabrication of resistor structures and gate electrodes is integrated. For example, a polysilicon line is patterned on a substrate by blanket deposition and subsequent etching. Thereafter, certain portions of the polysilicon line are set aside for gate electrode functionality while other portions are set aside as resistor structures. The gate electrode portions will normally be provided with some concentration of impurity doping to render those portions conductive and with a refractory metal silicide film that provides enhanced ohmic contact with later formed contact plugs. The resistor structure portions of the poly line will generally be left undoped and without a silicide film.
Many modem integrated circuits implemented on a semiconductor substrate consist of a plurality of active regions generally circumscribed and defined by isolation structures. The upper surfaces of the active areas and the surrounding isolation structures are generally non-planar. Indeed, the transition from active area to isolation structure involves a step height difference. This non-planarity produces a non-planar topography for later deposited films on the active regions and the isolation structures. This non-planar topography can result in the formation of so-called xe2x80x9cstringersxe2x80x9d on certain portions of the upper surfaces of polysilicon lines set aside for gate electrode formation.
In some conventional fabrication processes, a polysilicon line is blanket deposited on a substrate and subsequently masked to define the general shapes of a plurality of polysilicon lines. Thereafter, an anisotropic etch is performed to define the polysilicon lines. Next, an oxide film is formed over the polysilicon lines. The oxide film serves to mask selected portions of the polysilicon line to prevent silicidation thereof so that those unsilicided portions may serve as resistor structures. To this end, the selected portions of the oxide film on the polysilicon lines are masked with photoresist and the unmasked portions of the oxide film are anisotropically etched to the underlying polysilicon lines. As a result of the uneven topography of the polysilicon lines, particularly at the steps associated with the isolation structure to active area transitions, the anisotropic etch will not completely remove the oxide material from the polysilicon lines at those steps. Those stringers left behind represent portions of the polysilicon lines that may not form silicide during subsequent salicidation processing. If left unchecked, such stringers represent areas of potential undesirably high sheet resistance as well as poor contact plug adherence.
To alleviate the problem of stringers, conventional resistor protect etching processes incorporate one or more aggressive overetching steps in order to ensure that the stringers are removed. The difficulty associated with this conventional technique is the risk that one or more aggressive overetch processes will attack the isolation structure materials, particularly at the active area to isolation structure interfaces. This unwanted attack in those areas can lead to significant device leakage.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
In accordance with one aspect of the present invention, a method of fabricating a circuit structure is provided that includes forming a silicon structure on a substrate and forming an oxide film on the silicon structure. A first portion of the oxide film is masked while a second portion is left unmasked. The second portion of the oxide film is removed by isotropic plasma etching to expose a portion of the silicon structure, and the first portion of the oxide film is unmasked.
In accordance with another aspect of the present invention, a method of fabricating a resistor structure on a substrate is provided that includes forming a polysilicon structure on the substrate and forming an oxide film on the polysilicon structure. A first portion of the oxide film is masked while a second portion thereof is left unmasked. The unmasked portion of the oxide film is removed by isotropic plasma etching to expose a first portion of the polysilicon structure. A second portion of the polysilicon structure remains covered by the first portion of the oxide and defines a resistor structure. A silicide film is formed on the first portion of the polysilicon structure. The first portion of the oxide film prevents silicide formation on the second portion of the polysilicon structure.
In accordance with another aspect of the present invention, a method of fabricating a circuit structure is provided that includes forming a polysilicon structure on a silicon substrate and forming an oxide film on the polysilicon structure. A first portion of the oxide film is masked while a second portion thereof is left unmasked. The second portion of the oxide film is removed by isotropic plasma etching to expose a portion of the polysilicon structure, and the first portion of the oxide film is unmasked.